The present technique relates to an apparatus and method for estimating a shift amount when performing floating-point subtraction.
It is common to use floating-point (FP) representation in data processing systems. A floating-point number includes a significand and an exponent indicating a significance of the bits of the significand. A normalised floating-point number has a significand of at least 1 and less than 2, and hence has the format 1.xxxxx. When subtracting one floating-point number from another, the result can be a very small number, i.e. there can be a large number of leading zeros. In order to seek to renormalize the significand of the result, a left shift operation can be performed on the difference value obtained by subtracting one significand from the other significand.
It is known to use leading-zero anticipator circuitry (an LZA circuit) to seek to predict how many leading zeros there will be in the difference value, based on an analysis of the significands, with that leading zero information being used to determine a left shift to apply to the difference value in order to seek to normalise the difference.
However, normalisation for numbers less than 1.0 requires that the exponent be decremented to compensate for the adjustment being made to the difference value. Exponent decrementing becomes a problem when the exponent is already small, because FP numbers cannot have a true exponent below a predetermined minimum value. Accordingly, any proposed left shift produced by the LZA needs to be qualified, so that a left shift will not be applied that results in the exponent being decremented below the minimum value.
It would be desirable to provide an efficient mechanism for performing such qualification of the shift amount produced using circuits such as LZA circuitry.